This description relates to characterization and reduction of variation for integrated circuits. In fabricating integrated circuits, interconnect film thickness uniformity, dishing and erosion are dependent on variation in layout patterns (e.g. material density, linewidth and linespace). Surface non-uniformity often leads to subsequent manufacturability and process integration issues. These pattern dependencies may also affect device performance by introducing variation in capacitance and resistance depending on the location of a given structure on the device.
Film thickness variation in chemical mechanical polishing (CMP) processes can be separated into various components: lot-to-lot, wafer-to-wafer, wafer-level, and die-level. Oxide thickness variation due to CMP is mainly due to differences in layout patterns on the chip. Often, the most significant component is the pattern dependent or die-level component. The oxide is generally polished until all areas on the chip have been planarized. However, differences in the underlying metal pattern result in variation in the post CMP oxide thickness, even though a locally planar layer of oxide is achieved with CMP.
For oxide polishing, the major source of variation is caused by within die pattern density. Pattern density is defined as the ratio of raised oxide area divided by the total area of the region. The region may be taken as a square with the length of the sides equal to some length, the planarization length. The planarization length is usually determined by process factors such as the type of polishing pad, CMP tool, slurry chemistry, etc. The effective pattern density may be computed for each location on the die by filtering the designed layout densities, often by using various two-dimensional filters of densities around the given location.
For metal polishing in a damascene CMP process, other physical layout effects such as the linewidth and linespace may also be required. Two effects known as dishing and erosion result from metal damascene CMP. Dishing is measured as the difference in metal thickness at the edge of a line and its center. Erosion is defined as the difference in oxide thickness above a metal line, typically within an array of lines, to an adjacent unpatterned region. FIG. 2A shows the desired result of CMP in a damascene process where the copper features, 1 and 2, in the oxide field, 4, meet the desired wafer surface, 3. FIG. 2B shows the effects of the layout pattern on metal thickness variation in a damascene CMP process where the desired wafer surface, 5, does not match the actual wafer surface, 6. FIG. 2B shows the effects of Cu CMP dishing, 7, in a wide line as well as the effects of erosion, 8, in an array of fine pitch lines. These figures illustrate that other physical layout parameters, in addition to pattern density, are required to predict the variation in a damascene CMP process.
Dummy fill structures can be added to improve process uniformity. Adding metal dummy fill increases the pattern density since density is defined as the amount of metal divided by the total area within a given region. Conversely, adding oxide dummy removes sections of the copper line and decreases the pattern density. The addition of fill can also alter other parameters such as linewidth and linespace. If dummy metal is inserted between two parallel lines, the linespace changes for both of those lines. Similarly, if oxide dummy is inserted within a wire, its effective linewidth is changed. By modifying the existing layout through the addition of dummy fill, physical parameters such as pattern density, linewidth, and linespace are changed. Since metal or oxide film thickness non-uniformity resulting from CMP is dependent on these physical parameters, the addition or removal of metal alters the physical characteristics of the designed layout. Therefore, the addition of metal or oxide fill based on process models can reduce the film thickness non-uniformity.
Dummy fill is a method of improving film thickness uniformity in integrated circuits through the addition or removal of existing structures. The following two figures illustrate two types of dummy fill, metal and oxide. FIG. 2 illustrates the use of metal dummy fill. FIG. 2C shows a series of metal lines, 10, in an oxide layer, 9, with a large oxide field region in the middle, 11, that is available for dummy fill. One goal of dummy fill is to achieve uniform pattern density everywhere so that deposition and polishing process result in a planar film thickness. As such, this area would be selected as available for dummy fill. This region is particularly attractive in that it is of sufficient distance from electrically conducting lines and may minimize the impact of dummy fill on capacitance. In FIG. 2D, metal dummy fill, 14, has been placed in the oxide field area, 13, to raise the density of this region, while the metal dummy fill remains electrically isolated from the conducting regions, 12, around it.
FIG. 3 illustrates the addition of oxide dummy fill in a metal field. In FIG. 3A, metal field region, 15, has a large area, 16, available for oxide dummy fill. In FIG. 3B, oxide dummy fill (also referred to as metal slotting), 18, is added to the metal area, 17, raising the density of raised area of the region and subsequently improving the polishing uniformity (reducing the film thickness variation) of this region. The term “dummy fill area” is used to refer to the area where dummy fill is added and the term “dummy fill structures” is used to refer to the new objects that are embedded within that area.
Dummy fill may be placed using a particular placement pattern to reduce the impact of its presence within either a conducting or insulating structure. FIG. 4 shows three different dummy fill patterns. The first panel, FIG. 4A shows symmetric fill structures that are commonly used when oxide fill is placed in metal. The symmetric pattern promotes the flow of current through the metal region. The second and third panels, FIG. 4B and FIG. 4C, show asymmetric patterns that are commonly used when metal fill (i.e. a conducting material) is placed in an insulating material (e.g. oxide). The asymmetric nature retards the capacitive coupling between adjacent signal lines more than a symmetric pattern, resulting in reduced cross-talk noise. Designers desire that the addition of dummy fill not alter the desired electrical performance. However, the addition of dummy structures may unintentionally affect the electrical properties and degrade chip performance. Important factors must be considered for effective dummy fill. These factors include process effects, electrical effects, and placement impact.
The electrical performance of a circuit can be determined by the electrical characteristics of its interconnect, and the interconnect is often the limiting factor in high performance designs. These electrical parameters include the interconnect resistance and capacitance. Circuit performance metrics such as signal delay, clock skew, and crosstalk noise are functions of the interconnect resistance and capacitance. The interconnect resistance is a function of the wire resistivity, metal thickness, interconnect length, and linewidth. The interconnect capacitance is a function of the metal thickness, interconnect length, linewidth, linespace, and dielectric constant of the insulator (oxide) between the wires. Note that the geometry of the interconnect structures impact their electrical properties. Therefore, any variation in the geometry, such as the insertion of dummy fill or slots, may also affect the electrical performance metrics.
The addition of dummy fill can result in unwanted electrical effects. Adding dummy features alters the effective pattern density and linespace. Removing features (oxide fill) alters the effective pattern density and linewidth. The impact of fill depends on the designed interconnect structure neighboring the fill (for metal dummy) or the designed interconnect structure itself (for oxide dummy). Adding metal fill modifies the coupling capacitance (C) between neighboring interconnects. Adding oxide dummy modifies the coupling capacitance (C) and interconnect resistance (R). The relative impact depends on the dimensions of the interconnect structures. The level of variations in R and C determine how the circuit is affected.
Design rules can be constructed such that an acceptable level of variation tolerance is set for the interconnect RC variation. Alternatively, design rules can be set to allow a certain tolerance level for the circuit performance metrics such as signal delay, clock skew, or crosstalk noise. These performance metrics are normally functions of the interconnect RC. The total interconnect capacitance is heavily dependent on neighboring structures. These structures can be described as a canonical set where an object or class of objects is uniquely identified or standardized within a set of features (such as linewidth, linespace or density) related to process variation. Therefore, a dummy fill strategy should account for these electrical effects in addition to the process uniformity specifications relative to these features.
A short flow damascene process using ECD and CMP is shown in FIGS. 5 & 6. FIG. 5A illustrates step 1, where trenches, 19, are created in oxide for the interconnect structures using lithography and etching. FIG. 5B shows the early stage of step 2 where electroplating is used to fill the trench, 23, in field oxide, 20, from time T0, 21, to T2, 22. FIG. 6A shows the end at time Tf, 26, of step 2 where electroplating fills the trench, 27, in the field oxide, 24. FIG. 6B illustrates how CMP is used to remove the copper such that the trench, 28, is planar with the field oxide, 29.
Once the copper is deposited, it must be polished until all of the copper above the field regions is cleared. CMP is the leading method of copper removal and planarization in semiconductor manufacturing processes. Differences in the structures and their surroundings result in variable polish rates across the chip. To guarantee that there are no shorts between interconnects, over-polishing is done until all the copper is cleared above the field oxide. This results in metal thickness variation (see FIG. 4). Another application of dummy fill is to modify the interconnect structures and surrounding areas to reduce the variation. This can be done by adding metal dummy fill between the interconnect regions or removing metal from the existing interconnect. As such, the layout can be altered from its original design by adding additional features (metal dummy fill) or removing sections of existing features (slotting with oxide dummy fill). This improves process uniformity but can adversely affect the electrical performance of the chip. Therefore, the goal is to fill the layout in a way that reduces the process variation while preserving the original intended functions of the circuit.
In fabricating integrated circuits, interconnect features are dependent on variation in layout patterns (e.g. material density, linewidth and linespace). Surface non-uniformity often leads to subsequent manufacturability and process integration issues. These pattern dependencies may also affect device performance by introducing variation in capacitance and resistance depending on the location of a given structure on the device.
Lithography mask creation and printing assume that projection is done on a film, within a predetermined depth of focus range. However pattern dependencies between the process by which the ICs are fabricated and the pattern that is being created often cause processed films to have significant variation in thickness across a surface, resulting in variation in feature dimensions (e.g. line widths) of integrated circuits (ICs) that are patterned using the mask. As successive non-conformal layers are deposited and polished, the variation becomes worse. Because interconnect lines and connections on higher layers carry power to portions of the chip, the variations can increase the sheet resistance and thus affect the power effectiveness of the chip.
The characterization of feature thickness and width variation due to pattern dependencies in the deposition, etch, plating and polising processes, may be used to generate a full three-dimensional model of circuit features for each of multiple levels in a device. This model may be helpful in predicting the electrical performance of interconnect levels. The thickness and width variation of interconnect features has large impact on timing, propagation delay and power performance of the manufactured circuit.
One way to reduce the propagation delay is to use intermediate buffers (also known as repeaters) in longer interconnect wires. However it is often difficult to estimate the number and size of buffers needed, so designers are often overly conservative in their use of buffers which increases power consumption.
One way to reduce the variations in fabricated chips is to make physical measurements on manufactured wafers containing initial designs of devices and use these measurements to adjust the mask design. Other methods to reduce variation include optical proximity correction (OPC) where subwavelength distortions due to patterned features are identified and corrected.
One way to characterize variation in fabricated chips is through metrology. Metrology involves the measurement of silicon wafers, for example, in three different modes of operation: in-line operation in which wafer measurements are performed between process steps, in-situ operation in which the wafer is measured during processing, and off-line operation in which the wafer is removed from the process line for measurement. Metrology is an important operation in the introduction of new materials, processes, and structures associated with reduction of integrated circuit feature sizes. Metrology is also important for improving yield in mature fabrication lines. Through better characterization of variation due to process tools and processes, metrology can be used to reduce time-to-market and cost-of-manufacturing.
Measurements are often performed during the processing of an integrated circuit to gauge whether a process or process flow will result in the intended integrated circuit. The term metrology refers to the tools that make physical measurements on test and production wafers as well as the strategies for determining where on the wafer or die those measurements are to be taken. Measurement strategies may include measuring a particular group of sites on a die or across the wafer in a particular pattern or on particular structure within the die. Performing the measurements between process steps allows for easier isolation of a problem to a particular step and feature versus measuring the final circuit and then trying to diagnose which of 20 or 30 process steps caused the problem.
In determining which sites or locations to measure within a particular chip or die and which die to measure from among the multiple dies across the wafer, several factors come into play. Making too many measurements delays subsequent processing of the wafer, thus directly affecting manufacturing throughput and process yield. Making too many measurements may also produce too large a volume of raw data for a process engineer or diagnostic system to analyze in real-time.
As shown in FIG. 101A, test structures or devices 16025 are sometimes created on the wafer outside the circuitry of the chip, normally in scribe or kerf lines 16023, and the metrology is focused on those test structures or devices. The isolated test structure 16025 may not resemble the features 16029 in the IC design 16024 that entail a problematic variation.
If pattern dependencies, such as density, linewidth, and linespace cause variation in electrical performance, a feature and its surrounding features may need to be measured. Interactions between vertical layers may also need to be considered. These considerations may grow in importance as different types of circuitry are consolidated densely onto a single chip, for example, in a mixed mode system-on-a-chip (SOC) design 16024 in which analog, logic, I/O, and RAM components are designed into one chip.
The fabrication of an integrated circuit device typically involves a cycle of design and manufacturing until the fabricated device resembles, both physically and electrically, that which has been designed. Much of the complexity is due to the constraints that not all designed circuits can be manufactured and not all manufactured circuits perform as designed or simulated.
As such, a cyclic process is initiated whereby circuits are designed, layer-by-layer using electronic design automation (EDA) software, expensive masks are built for printing the circuit on the wafer via lithography and a series of costly manufacturing steps are run to fabricate the final device. The device is measured throughout fabrication and circuit performance is finally characterized. This information is used to grade the device and often several cycles are needed to modify the design and process settings until the device reaches acceptable performance or achieves the design specifications. Each design-manufacturing cycle requires costly manpower and materials as well as impacting time-to-market for each new device.
The fabrication part of the cycle normally requires experimental design and recipe generation for each step in the process flow. Often a design of experiments is used to select a number of process settings that will be used to characterize a particular tool for a particular IC device. Typically these experiments and subsequent process optimization tasks are done after a device has been taped-out and all the prior fabrication steps have been performed. Thus, a number of wafers are processed at specific equipment settings, measured for physical and electrical characterization and a process setting is chosen that best fits the desired IC criteria. This is repeated for each step in the flow. At some point, the process variation often compounds from one process step to another until it is determined that there are no process settings that can achieve the objective and a chip cannot be manufactured reliably. This is an expensive and time-consuming process to determine the manufacturability of a given design.
Manufacturability is not purely an afterthought. The experience and knowledge of the process engineers are often captured in design rules to prevent such occurrences before a new IC design is taped-out and manufactured; however, new devices still normally require repeated design and manufacturing cycles. The reason for this is that the design rules are often based on manufacturing experience gained from prior devices and technology generations and the experience may not be synthesized, taking into consideration the sequential impact of individual process steps that constitute the complete process flow. Much time and resources are spent developing linear and nonlinear optimization methods that characterize the impact of variation on one or more process steps. However, these approaches do not adequately address problems associated with generating the initial design rules and assessing the manufacturability of an IC in the design stage.
The increased cost and complexity of developing a new semiconductor product necessitate that the timeframe for new process introduction to achieve reasonable quality must decrease. Advances in circuit design (e.g. ASIC) and factory architecture and control have had significant impact toward cost effective and timely production of new integrated circuit (IC) structures; however IC process design remains the pacing item in shorting cycle times and achieving lower non-recurring engineering costs.
Process synthesis is top-down hierarchical approach to process design where device performance and design requirements are used to determine overall process flow and individual process recipes. The approaches vary from the use of known and understood device structures and process flows to custom or new device architectures where the process flow and recipes are derived from device design parameters and advanced process models.
As shown in FIG. 129, levels of abstractions provide a top-down hierarchy where the system 16602 can be designed in an ordered fashion without addressing the details at lower levels (16604-16606). However the designer requires that the specifications at higher levels are consistent with those at lower levels. A goal of synthesis and simulation tools is to not only translate specifications but also manage constraints and conflicts to achieve a global solution for a process flow. In this context, a process flow may be defined as three polishing steps; bulk polish, endpoint and barrier removal. Process flow may also include all the etch, litho, deposition, plating and polish steps in the creation of an IC. In this approach, synthesis is used translate the specifications from a higher-level abstraction to a structure at the next lower level that meets those specifications.